The present invention relates to a semiconductor packaging process, and more particularly to a SOC (Substrate On Chip) packaging process.
The so-called xe2x80x9cSOC packagingxe2x80x9d, which is Substrate-On-Chip packaging for short, is referred to a semiconductor packaging structure in common use. Semiconductor chips are attached on a substrate with holes, and a plurality of metal bonding wires connect the substrate with the chips via the holes. Normally the substrate is also formed with a plurality of solder balls in a grid array. In the U.S. Pat. No. 6,190,943 entitled xe2x80x9cCHIP SCALE PACKAGING METHODxe2x80x9d, a SOC package structure and a packaging method are disclosed. As shown in FIG. 1, the SOC package 20 comprises a wiring substrate 22, a semiconductor chip 24, and a plurality of spherical bonding balls 44. The substrate 22 has an upper surface 30 for attaching the chip 24, an underside 38 with the spherical bonding balls 44 implanted therein, and through holes 34 passing through the upper surface 30 and the underside 38. Wherein the chip 24 is attached to the upper surface 30 of the substrate 22 by a thermoplastic adhesive layer 28. The through holes 34 of substrate 22 expose the bonding pads 36 of the active surface 26 on chip 24 so that the bonding wires 32 may connect the bonding pads 36 of the chip 24 and the conductive area 41 of substrate 22 via the through holes 34. The conductive area 41 is provided with a conductive layer 40 formed on the underside 38 of substrate 22. The fringe of the chip 24, and each of the through holes 34 of substrate 22 are protected by a passivation layer 42 of a non-conducting resin material.
As shown in FIG. 2, the method for making the SOC package structure 20 disclosed in the U.S. Pat. No. 6,190,943 entitled xe2x80x9cCHIP SCALE PACKAGING METHODxe2x80x9d comprises the steps of: (a) providing a substrate 22 with an upper surface 30 which is provided with at least one chip-implanting area 302 including the through holes 34 mentioned above; (b) coating a thermoplastic adhesive layer 28 on the chip-implanting areas 302 by stenciling; (c) implanting chips 24 in the area 302 such that the active surfaces 26 are in contact with the thermoplastic adhesive layer 28, and that the bonding pads 36 are corresponding in location to the through holes 34; (d) heating the substrate 22 and the chips 24 under pressure for a predetermined period of time; (e) forming the bonding wires 32 connecting the conductive area 41 of the substrate 22 with the bonding pads 36 of the chips 24 by wire-bonding via the through holes 34; (f) providing a passivation layer 42 on the fringe of the chip 24 and the through holes 34; (g) implanting a plurality of bonding balls 44 in a grid array on the underside 38 of the substrate 22. The SOC package structure 20 is therefore completed by following the above-mentioned steps. The thermoplastic adhesive layer 28 mentioned in step (b) is an elastic, semi-liquid, solvent-free thermoplastic silicon rubber. Because it is semi-liquid before attachment, therefore the heating and pressuring conducted the thermoplastic adhesive layer 28 in step (d) is easy to overflow and thus cover the bonding pads 36 of the chip 24, causing failure in packaging. It is still another disadvantage that after coating of the thermoplastic adhesive layer 28 in step (b), it is unable to pile the substrates 22 for delivery or storage. It has to have the thermoplastic adhesive layer 28 attach to the chips 24 as soon as possible, otherwise, the substrates 22 will be contaminated and adhere to each other, causing difficulties in manufacture.
A main purpose of the present invention is to supply a SOC packaging process, utilizing a layer of two-stage thermosetting mixture with solvent coating on an upside of a substrate for chip-attachment. After the substrate is heated for removing solvent, the two-stage thermosetting mixture becomes a dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better manufacture quality is obtained in the SOC packaging process.
A second purpose of the present invention is to supply a SOC packaging process, utilizing a layer of two-stage thermosetting mixture with solvent coating on an upside of a substrate for chips attachment. After the substrate is heated for removing solvent, the two stage thermosetting mixture becomes a dry adhesive film without solvent. Thus, the substrates with dry adhesive films are able to pile for delivery or storage, and a better operating flexibility is attained in the SOC packaging process.
The SOC packaging process in accordance with the present invention comprises a first step in which a substrate is provided with an upper surface, an underside surface, and openings which connect the both. Thereafter, the upper surface of the substrate is coating with a two-stage thermosetting mixture with solvent by stenciling or printing. The thermosetting mixture with solvent is subsequently heated and to become a dry adhesive film. Then, at least a chip is provided with an active surface and a plurality of bonding pads disposed on it. Wherein the active surface is in contact with the upper surface of the substrate, and the bonding pads of the chip are corresponding in location to the openings of the substrate. Thereafter, the substrate and chip are heated under pressure to solidify the dry adhesive film so that the chip is securely attached to the substrate. Then the bonding pads of the chip are electrically connected to the substrate by wire-bonding via the openings. Finally, an encapsulating material is provided on the openings of the substrate and, if necessary, a plurality of bonding balls could be implanted on the underside of the substrate to comprise the SOC packaging process.